Server data from the Official MCP Registry
AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
AI-agent MCP server for FPGA design: compile, validate & generate Verilog from C⏚ HDL.
A well-structured MCP server for FPGA/HDL design with solid security fundamentals. The code properly isolates compiler invocations in temporary directories, avoids hardcoded secrets, and validates file operations against a project root. Minor code quality issues and a dependency on an external JAR file introduce low-severity concerns, but permissions align with the server's stated purpose of driving an HDL compiler toolchain. Supply chain analysis found 3 known vulnerabilities in dependencies (0 critical, 3 high severity). Package verification found 1 issue.
4 files analyzed · 11 issues found
Security scores are indicators to help you make informed decisions, not guarantees. Always review permissions before connecting any MCP server.
This plugin requests these system permissions. Most are normal for its category.
Set these up before or after installing:
Environment variable: CG_JAR
Add this to your MCP configuration file:
{
"mcpServers": {
"io-neosyn-cg-agent-kit": {
"env": {
"CG_JAR": "your-cg-jar-here"
},
"args": [
"cg-agent-kit"
],
"command": "uvx"
}
}
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